1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a two step process for forming spacers in a self aligned contact process which eliminates the key hole problem in the IPO (inter-poly oxide) layer.
2) Description of the Prior Art
The use of self aligned contact (SAC) processes has resulted in higher performing, lower cost, and increased density semiconductor devices. A self aligned contact process spacers are formed on the sidewalls of conductive structures (such as gates and bit lines); and IPO layer is formed over these conductive structures; a contact opening is etched through the IPO; and a conductive layer is formed over the conductive structures and in the contact opening. However, as device dimensions and die sizes continue to decrease for higher density, the space between adjacent conductive structures becomes narrower. The surface of the sidewall spacers facing the contact opening become concave (overhang) which leads to voids or key holes in the subsequently formed IPO layer. The key holes can cause two separate devices (such as capacitors) which are formed over the IPO layer to short, resulting in cell failure.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,747,373 (Yu) shows a method of forming a first SiN spacer and a second oxide spacer.
U.S. Pat. No. 5,208,472 (Su et al.) shows a double dielectric spacer. The first is oxide and the second is of a dielectric material.
U.S. Pat. No. 5,827,782 (Shih) shows a method of optimizing an IMD spacer layer profile.
U.S. Pat. No. 5,789,314 (Yen et al.) shows an IMD layer method with an etchback of an oxide layer.
U.S. Pat. No. 5,296,092 (Kim) teaches a planarization method where an upper portion of the oxide layer is etched back.